Buffered program operations are used in memory devices, such as flash memories. Typically a buffered program operation allows multiple words, typically up to thirty-two words, to be programmed without wait states. In order to do so, an internal buffer is used. The internal buffer is used because physical programming operations are typically much slower than external timing.
In order to perform buffered programming, a write setup command is typically provided to the internal buffer. Words may then be sent to the internal buffer. In addition, the address of the first word is provided. The words are then temporarily stored in the internal buffer, then written to the memory.
In order manage the words written to the internal buffer, internal address bits are generated to define the words' positions in the internal buffer. For internal buffers capable of writing thirty-two words, five internal address bits A0, A1, A2, A3 and A4 are used. In addition, another bit, the A5 bit, termed a group bit herein, may be used to indicate a particular group of words stored in the buffer. Using the internal address bits, the internal buffer can reference the words to be written.
The addressing scheme can be used for performing aligned buffered program operations because A5 is the same for all words being programmed. However, one of ordinary skill in the art will readily recognize that misaligned buffered program operations are problematic. In particular, misaligned buffer operations may write different groups of words. Thus, in misaligned buffered program operations, the A5 bit can change. A mechanism for accounting for the changing value of the A5 bit needed.
FIG. 1 depicts a conventional double internal buffer 10 used in performing misaligned buffered program operations. The double internal buffer 10 includes two buffers 20 and 30. For the buffer 20, thirty-two locations 21 are provided for storing up two thirty-two words. Also depicted are validity bit locations 22 that are used for storing a validity bit for each of the locations 21. Similarly, for the buffer 30, thirty-two locations 31 are provided for storing up two thirty-two words. Also depicted are validity bit locations 32 that are used for storing a validity bit for each of the locations 31. For the buffer 20, bits A0, A1, A2, A3, and A4 are used for internal addressing. Similarly, for the buffer 30, bits A0, A1, A2, A3, and A4 are used for internal addressing. Bit A5 is used to select between buffer 20 and buffer 30. For the first buffer 20, the bit A5 is a zero. For the second buffer 30, the A5 is a one. Because two buffers 20 and 30, each of which uses internal addressing, are utilized, misaligned buffer operations in which the words from both buffers 20 and 30 having different values of A5 can be performed. In particular, the word to be programmed in a memory location which has A5=1 will be stored in the buffer 30, the word to be programmed in a memory location with A5=0 will be stored in the buffer 20.
Although the conventional internal double buffer 10 allows for misaligned buffered program operations to be performed, one of ordinary skill in the art will readily recognize that the conventional internal double buffer 10 has significant drawbacks. The conventional internal double buffer 10 consumes significantly more circuit area than a conventional internal buffer that is a single buffer. In addition, buffered program operations take longer to complete. This is because a user can perform buffered program operations without being effectively limited in the number of programmable words. Thus, it cannot be determined whether a particular buffer 20 or 30 contains a valid word to be programmed without reading the entire double buffer 10. Thus all of the locations 21 and 31 in the double buffer 10 are traversed and it is determined, using the validity bit, whether each of the locations 21 and 31 stores a word to be programmed. Consequently, not only does the conventional double internal buffer 10 consume more space, but is also requires a longer time to complete a programming operation. Note that it is not necessary to memorize the A5, A4, A3, A2, A1 and A0 address bits of the word to be programmed because this information is obtained by the word position in the buffer 10.
Accordingly, what is needed is a mechanism for more efficiently performing misaligned buffered program operations while allowing the internal buffer to consume less area. The present invention addresses such a need.